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Applying Microelectronics Upgrading the Perimeter Acquisition Ranging and Characterization System (PARCS) Radar June 1999
MITRE's Center for Air Force C2 Systems is well known for providing its customers with innovative, resourceful solutions to some of their most challenging technical dilemmas. The MITRE Microelectronics Center, one of a dozen technical centers within The MITRE Corporation, developed an advanced design capability under the Emerging Technologies for Very Large Scale Integrated Circuit (VLSI) Applications project of the MITRE Technology Program. MITRE staff then used these capabilities to evaluate, design, develop, and test an Application Specific Integrated Circuit (ASIC) chip using VLSI technology. Here's how they did it. The Problem The US Air Force operates a Perimeter Acquisition Ranging and Characterization
System (PARCS) in Cavalier AFB, North Dakota that included a rapidly deteriorating
set of Dispersive Delay Lines (DDL) in the radar's pulse compression signal
processing equipment. These analog DDLs expand and compress their FM chirp
waveforms. This acoustic-based equipment, some of which dated back to
the 1970s and is no longer manufactured, survived far beyond its design
life through multiple repairs. Since no commercial contractors were willing
to build a replacement, the Air Force asked MITRE to evaluate the problem
and recommend a solution.
Building a Prototype The project began in 1996 when several MITRE staff completed a preliminary study to examine the PARCS radar problem. The study concluded that several technologies could be used as a replacement. However, digital signal processing offered the best mix of low cost, easy maintenance, and reproducibility. In 1997, MITRE staff completed a more comprehensive study that examined the system requirements for a digital replacement. Because COTS products could not provide the necessary processing speed, a group of teams consisting of members of the Microelectronics Technical Center, the Communications and Networking Directorate, and the Sensors and Enabling Technologies Directorate was formed that could provide the collaborative effort necessary for building and testing a prototype. Fewer than 10 staff members made up the ASIC team, the system level design team, the analog design team, and the reliability and testing team. Their assignment was to develop a prototype replacement that would work as a drop-in functional replacement for the current analog lines. In addition, the radar circuitry surrounding the new delay line could not be redesigned, so the digital delay line had to meet all the existing radar specifications. Less than six months later, the ASIC team finished the design of a 1.3 million transistor chip for the MITRE-developed prototype. This custom VLSI signal processing chip performs a 1024-tap finite-impulse response (FIR) filter running at an estimated 2 million samples per second (Msps). The configurable architecture of the ASIC allows the number of FIR filter taps to be traded for sampling rate and could be useful in other radar and communication systems. To accomplish a throughput comparable to this chip with a general-purpose microprocessor (e.g. Pentium or PowerPC processors) or a digital signal processor (e.g. TMS320), the processor would need to run faster than 10 GHz, clearly far beyond what was available in 1997. Key to MITRE's success in evaluating the PARCS radar problem and developing a solution was the collaborative effort of the many individuals involved in the project. Instead of "working in a box," the teams worked in parallel. This collaboration facilitated the identification and rectification of potential problems early in the design and development process. The multi-disciplinary talents of MITRE's engineers also played a key role in the final product specification of such a large transistor chip in less than half a year. People Behind the Project
The PARCS project was truly a cross-discipline effort that involved resources and expertise from a number of MITRE specialty groups. Here is what some of the PARCS team members say about their work on the project. "The PARCS DDL replacement project is an excellent demonstration of the value of MITRE and its people. The project team applied a broad range of skills to tackle a job no other company was willing to take on. They analyzed the problem from every view and crafted a solution using current COTS technology that reduces maintenance costs, increases reliability, and maintains the performance of a critical legacy system." Dale Earl, PARCS DDL task leader. "MITRE designed a replacement using state-of-the-art integrated circuit (IC) technology and field programmable gate arrays. The ICs we delivered had over 1 million transistors and were designed by 4 staffmembers in less than 6 months. That is a fraction of the staffing other companies use to develop custom ICs of that complexity and we still did it in a short period of time. This chip performs 6,000,000 operations per second, which is about 100x more than the fastest Pentium processor could deliver at the time." Roberto Landrau, PARCS radar ASIC team. "While on site in North Dakota, we saw what a very powerful asset the PARCS radar still is. Despite its age, the equipment provides a valuable service to the DOD and NASA. Upgrading it to digital technology just makes it better." Ed Ostroff, preliminary study team. "We had a challenging systems engineering role to perform for this project. There was no specification for the job so we had to create one. We had to determine exactly how the old part worked in order to write the specification for a new part that could incorporate the optimal solution—using advanced digital technology." Daniel Moulin, PARCS radar system-level design team "Since radar is one of the few areas that utilizes high resolution analog design, the PARCS project gave me the opportunity to work on the design of a very reliable, high resolution functional system." John Psilos, PARCS radar analog design team.
Page last updated: April 15, 1999 | Top of page |
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