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Scalability Simulations for Nanomemory
Systems Integrated on the Molecular Scale
2003 Award Winner
Matthew M. Ziegler, The MITRE Corporation
Carl A. Picconatto, The MITRE Corporation
James C. Ellenbogen, The MITRE Corporation
André Dehon, The Calilfornia Insitute of Technology
Deli Wang, Harvard University
Zhaohui Zhong, Harvard University
Charles M. Lieber, Harvard University
ABSTRACT
Simulations were performed to assess the prospective performance of
a 16 Kbit nanowire-based electronic nanomemory system. Commercial off-the-shelf
microcomputer system modeling software was applied to evaluate the operation
of an ultra-dense storage array. This array consists of demonstrated
experimental non-volatile nanowire diode switches, plus encoder-decoder
structures consisting of demonstrated experimental nanowire-based nanotransistors,
with nanowire interconnects among all the switching devices. The results
of these simulations suggest that a nanomemory of this type can be operated
successfully at a density of 1011 bits/cm2. Furthermore, modest device
alterations and system design alternatives are suggested that might
improve the performance and the scalability of the nanomemory array.
These simulations represent early steps toward the development of a
simulation-based methodology to guide nbanoelectronic system design
in a manner analogous to the way such methodologies are used to guide
microelectronic system design in the silicon industry.
» Download Paper [PDF, 1.6MB]
Publication
Annals of the New York Academy of Sciences, Volume 1006, Molecular
Electronics III, pp. 312-330 ©2003.
Additional Search Keywords
nanotechnology, nanoelectronics, nanocricuits, nanomemory, molecular
electronics, very-large-scale integrationl crossbar architectures, computer-aided
design
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