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Performance Simulation and Analysis of a CMOS/Nano Hybrid Nanoprocessor System
April 2009
Adam C. Cabe, The MITRE Corporation
Shamik Das, The MITRE Corporation
ABSTRACT
This paper provides detailed simulation results and analysis of the prospective performance
of hybrid CMOS/nano electronic processor systems based upon the Field-Programmable Nanowire
Interconnect (FPNI) architecture. To evaluate this architecture, a complete design was developed for
an FPNI implementation using 90-nm CMOS with 15-nm-wide nanowire interconnects. Detailed
simulations of this design illustrate that critical design choices and tradeoffs exist beyond those
specified by the architecture. This includes the selection of the types of junction nanodevices, as
well as the implementation of low-level circuits. In particular, the simulation results presented here
show that only nanodevices with an "on/off" current ratio of 200 or more are suitable to produce
correct system-level behavior. Furthermore, the design of the CMOS logic gates in the FPNI system
must be customized to accommodate the resistances of both "on"-state and "off"-state nanodevices.
Using these customized designs together with models of suitable nanodevices, additional simulations
demonstrate that, relative to conventional 90-nm CMOS FPGA systems, performance gains can be
obtained of up to 70% greater speed or up to a nine-fold reduction in energy consumption.
Publication
Nanotechnology, 20(16), 165203 (April 2009).
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