Methods, systems, and computer program products for rateless coding

The disclosed methods, systems, and computer-program products for compute a power allocation for a rateless, error-correcting code constructed from a plurality of repeated blocks having a plurality of superimposed layers and having a decoding signal-to-noise ratio (SNR) threshold. A noise threshold for an initial block of the rateless code is determined based on at least the SNR threshold, and a power allocation for each layer of the initial block is then calculated based on the determined noise threshold. The calculated power allocation may ensure that each layer of the initial block experiences the SNR threshold. Power is then allocated to each layer of a block proximate to the initial block such that each layer of the proximate block has an effective SNR equivalent to the SNR threshold. The allocating step for the proximate block is then repeated for each of the plurality of repeated blocks subsequent to the initial block to allocate power to each layer of the plurality of repeated blocks.

Patent #: 7869539 Issue Date: January 11, 2011